This post is the implementation part of the my post on RS code workout where I did some math workout on the RS forward-error-correcting code (FEC). I find it to be simple enough to implement it in verilog that can eventually be synthesized for FPGA. I choose the simplest algorithm to implement the RS (15,9,7) as outlined in my last post.
This post is the implementation part of the my post on Binary BCH (15,7,5) workout where I did some math workout on the BCH forward-error-correcting code (FEC). I find it to be simple enough to implement it in verilog that can eventually be synthesized for FPGA. I choose the simplest algorithm for decoding the binary BCH (15,7,5) as outlined in my last post.
This post is the implementation part of the my post on simple cyclic Hamming code where I did some math workout on this type of forward error-correction code (FEC). I am doing it for fun since I think it is simple enough to implement it in FPGA. The generator for this exercise is \(g(x)=1+x+x4\) for an \((n,k,d) \equiv (15,11,3)\) code.
My previous blog was to create the SPI slave device on Programmable Logic (PL) side of the Zynq7000 where it can be interconnected and can be accessible by the Processing System (PS) side of this SoC and I achieved the result I expected. Since that blog was only for validating my SPI slave design to be coherent with the rest of the system without doing much useful work, I would like to extend it so that I can make it do a bit more useful work.
I would like to add a simple IO peripheral device to the Zynq Zybo board and I would like to learn how much effort I need to get PS-PL interconnected and can be used by high level OS such as Linux. For this exercise, I choose to create a simplest device for the Zynq PL that interface with its PS. My choice is to create a SPI slave device (PL) that will interconnect to the SPI master of the Zynq (PS).
My previous blog was about displaying simple bar graph on a standard VGA 640x480@60HZ monitor using synthesized Verilog code. This blog is to follow on with that exercise, but using the actual sampled data from the Xilinx XADC instead.
Run-length encoding is one simple encoding, if not the simplest form of data compression. The more repetition in the data stream the better it is. For example, if input data stream is 'A2.A2.C1.C2.B4.B4.B4.B4.B4.B4.B4.B4' the output would be '02.A2.01.C1.01.C2.08.B4'. If there are 258 bytes of B4, then output would be '...FF.B4.03.B4'. In this experiment I simulated the flow of data stream and the encoding with verilog on the Nexys4DDR board, but first I should specify the specification of the implementation.
The Digilent Nexys4DDR has only one video port which is a VGA port. With a small set of verilog code, I can synthesize a simple circuit to draw some bar graph having each line with a width of one pixel. To achieve this I need to create the HSYNC and VSYNC for the desired output of 640x480@60HZ. The standard VGA of 640x480 is meant for its displayable area while it actually has 800x525 of total area. This makes the required pixel clock frequency of 800 * 60 * 525 = 25.200MHZ.
Servo motor is an electromechanical drive that is relatively simple to operate. A typically servo motor has relatively few movements, namely left, right and center. Controlling its movement is to send the periodic pulse width of about 1.5ms, 1ms or 2ms for the center, left, and the right movement respectively. In this demo, I use a very simple verilog code to control its movement.